Samtec to Participate in Upcoming Webinars

New years lead to new goals. As an technologist, I always need to stay on the bleeding edge. That’s require constant diligence, and it can be quite a challenge. Webinars always help.

As the calendar flips into 2026 new products, industry standards, design techniques and more are coming down the pike. As always, engineers, technicians, system architects and other technologists like me need to keep their skills sharp as design cycles shorten and time to market remains critical as ever.

To that end, Samtec will be participating in two upcoming webinars. One webinar will focus on the newly released VITA™ 93 QMC™ industry standard. VITA 93 QMC defines a flexible, next-generation mezzanine concept for small form factor modules. The second webinar target PCB design techniques target 28 Gbps, 56 Gbps and 112 Gbps performance. Keep reading for more details on each webinar.

Enabling Modular Rugged High-Performance Computing Applications

Rugged computing platforms in a number of applications ranging from commercial space, medical, automation and mil/aero demand solutions that are small, modular, high-performance, and able to operate in extreme environments. The VITA 93 QMC standard, developed by the VITA Standards Organization, will help solve many of these challenges and enable interoperability across multiple applications.

Technical experts from Samtec, New Wave Design, and Acromag are ideally suited to explore this topic in an upcoming webinar entitled VITA 93 QMC: Enabling Modular Rugged High-Performance Computing Applications.

Registrants and attendees will learn how the modular, stackable mezzanine architecture introduced by the VITA 93 QMC standard presents a rugged alternative to M.2 and Mini-PCI Express modules and offers solutions from basic serial I/O to high-performance signal-processing applications across multiple applications. Please join is for this timely topic.

High-Speed Success at 28-56-112 Gbps with Connector-PCB Integration

As data rates move beyond 28 Gbps and scale rapidly to 56 and 112 Gbps, the margin for PCB design error shrinks dramatically. At these speeds, connector-PCB integration, stack-up decisions, and via design are no longer secondary considerations; they directly determine transmission line insertion loss, return loss, and overall signal integrity. Connector selection and termination to the PCB also play a critical link.

At 28-56-112 Gbps, high-speed PCB design leaves no room for guesswork. Stack-up architecture, dielectric selection, and via-in-pad geometry directly impact channel behavior, where even a few mils of dielectric variation or a single unremoved via stub might be the reason behind a failed link.

In this webinar, you’ll learn the practical techniques for high-speed PCB design with connectors. It will help you meet signal integrity targets and avoid expensive production issues. Technical expert from Samtec and Sierra Circuits will provide a deep dive into this pertinent topic. Here’s a quick overview of the agenda:

• Stack-up design for 28-112 Gbps
  • Design and layout strategies to ensure uniform impedance
  • Dielectric choices to manage glass weave effects and loss
  • Techniques for maintaining reference plane continuity
  • Common stack-up mistakes we see 
  • How to design stack-ups that are manufacturable 
  • Stack-up examples
• Via design that doesn’t kill your channel
  • Via stubs and aspect ratio tradeoffs
  • Via-in-pad considerations for high-speed signals
• High-speed connector breakout region (BOR) design
  • Optimized signal launch from high-speed mezzanine connectors
  • Proper via design and placement optimized SI
  • Grounding techniques to minimize discontinuities
  • BOR design evolution from 28 Gbps > 56 Gbps > 112 Gbps

Click here to register and learn more.