Samtec is proud to sponsor the upcoming PCI-SIG Developers Conference 2023. Like last year, the event will be in-person with demonstrations, presentations and networking oppotunites. Past attendees agree that PCI-SIG DevCons are not to be missed!
PCI-SIG DevCons are free events for the 900+ PCI-SIG member companies like Samtec that develop and bring to market new products utilizing PCI Express® technology. They are an opportunity to learn directly from the industry’s PCIe® experts and participate in technical trainings to gain best practices to improve product roll-out and interoperability.
Dates and locations for the US PCI-SIG DevCon are shown below.
June 13-14, 2023
Santa Clara Convention Center
Santa Clara, CA
Attendee Registration – Now Open!
Online attendee registration is open for US DevCon. All employees of PCI-SIG member companies are welcome to attend this exciting conference!
Please make sure to visit with Samtec technical experts and product specialists to learn more about our copper ad optical PCIe interconnect solutions.
Technical Sessions
Samtec and our partners will be participating in two technical seesions at the PCI-SIG DevCon. Resident PCI Express technology expert Steve Krooswyk will detail exceptions of excusion compliance in cables and connectors.
Our friend Martin Stumpf from Rohde & Schwarz will detail the challenge of PCIe 5.0/PCIe 6.0 compliance in interconnect. This details the partership between Samtec, Rohde & Schwarz and Allion Labs on the topic. Details for the two presentations are below.
Cable and Connector Compliance with Integrated Return Loss
Steve Krooswyk – Tuesday, June 13 | 3:30 PM – 4:30 PM PT
Upcoming PCIe 5.0 and 6.0 Cable and 6.0 CEM specifications are considering Integrated Return Loss (IRL) for excursion compliance. Excursions may occur as compliance further reduces noise requirements and suppliers optimize high volume manufacturing practices. Excursions up to a limit have minimal system impact. IRL is not new, it’s history and process are reviewed, followed by simulation and measurement examples.
Connector and Cable Assembly Challenges for PCIe 5.0 and 6.0
Martin Stumpf – Wednesday, June 14 | 9:00 AM – 10:0 AM PT
With 32 GT/s in PCIe 5.0 and 64 GT/s in PCIe 6.0, channel characteristics like loss, reflections and crosstalk are increasingly critical for the overall system performance. We will discuss performance requirements and implementations of PCIe 5.0 / 6.0 connectors and cable assemblies and the corresponding test setups and measurement methods to characterize and verify these interconnects. New metrics of ICN and IRL are included, as well as the related measurements.
As the PCIe specifications define the performance requirements without the test fixtures, optimized test fixture design and accurate test fixture modelling and de-embedding is key for good measurement results. We will preview modern de-embedding techniques with accurate impedance modelling of lead-ins and lead-outs.
New PCI Express® 5.0/6.0 Solutions
Samtec has developed an updated PCI Express® Interconnect Solutions Guide. This new tool summarizes a number of solutions supporting the PCI Express® applications including:
- PCI Express® CEM AIC Solutions
- PCI Express® Capable Solutions
- Future-Proof 112 Gbps PAM4 Solutions
Samtec’s PCI Express® product line includes connectors, cable assemblies and PCIe® CEM AICs that help drive fast, efficient, point-to-point communication.
For more information on Samtec’s PCIe solutions, please visit www.samtec.com/pcie.
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