Samtec Showcases AI/ML Interconnect Demonstration at PCI-SIG Conference

The PCI-SIG Developers Conference is a free event for the 800+ member companies that develop and bring to market new products utilizing PCI Express® technology.

Granted most people reading this blog won’t be at the conference, but you might be interested in learning more about Samtec’s demos and Technical Sessions.

Demonstrations

Scalable 32 GT/s Silicon Test Platform: This is a demonstration of configurable, next-generation GPU-based system combining a cable mesh backplane (AcceleRate® Slim Body Cable Assemblies) and next-generation High-Speed Edge Card Connector topologies.

The demonstration incorporates an Artificial Intelligence, Machine Learning style interconnect based on the GenZ-PECFF form factor. The topology incorporates up to eight risers that include PCIe Gen5 AI usage models, and the Samtec Flyover® concept.

The system provides scalability of the PCB and cable interconnect via moving add-in cards and swapping cables, all operating within PCIe Gen 3, Gen 4, and Gen 5 performance requirements.

56 Gbps PAM4 Active Product Demonstrator: The 56 Gbps PAM4 Active Product Demonstrator showcases Samtec’s comprehensive portfolio of high-performance interconnect in a typical data center chassis application. 

Both of these demonstrations can be seen in the Samtec booth at the PCI-SIG Developers Conference 2019 at the Santa Clara (CA) Convention Center. 

Technical Sessions

Enable PCIe Express ® (PCIe ® ) 5.0 System Design with Ethernet Architectures (Kevin Burt, Senior System Architect, Samtec Optical Group): As PCIe technology data rates increase to 32 GT/s, system SI becomes critical. As other interfaces (Ethernet, InfiniBand, etc.) achieve higher data rates, opportunities exist to leverage industry-wide techniques that optimize power, thermal efficiency and cost-effectiveness across the system. Samtec will explore options enabling PCIe technology system architects to achieve similar results. (1:00 p.m., Tuesday, 18 June)

32GT/s Test Platform for AI and ML Implementations (Steve Krooswyk, Senior SI Engineer): Confident SI evaluation in emerging AI/ML form factors and cable mesh topologies requires realistic interconnect stress. Current length extenders and multiple PCIe topologies present challenges for adequate SI evaluation.  Samtec will present the advantages of next-generation Scalable 32 GT/s Silicon Test Platforms. (11:30 a.m., Wednesday, 19 June)

Click here for more information on Samtec high-performance interconnects. Please contact the Signal Integrity Group if you have other questions, or want to learn more about the presentations or demos.