PCI Express® (PCIe) is the backbone interface for connecting high-speed components in modern computing. Desktop PC motherboards connect to graphics cards, RAID cards, Wi-Fi cards or SSD add-on cards via any number of PCIe expansion slots.
Current desktop, laptop, server and gaming computing platforms leverage PCIe 4.0 (8 GT/s) infrastructure. Looking forward, chipsets solutions from Intel, AMD, Nvidia and others feature native PCIe 5.0 (16 GT/s) support. Also, PCIe 5.0 capable motherboards, SSDs and other components are popping up in the market.
PCIe performance never slows. PCI-SIG®, the industry association committed to advancing PCIe technology, is developing the latest PCIe 6.0 specification.
Is PCIe 6.0 Real?
The short answer is yes. PCI-SIG recently released the PCIe 6.0 specification, version 0.9. As with previous versions, the PCIe 6.0 specification doubles the data rate and maintains backwards compatibility.
Key features of the latest PCIe 6.0 specification include:
- 64 GT/s data rate and up to 256 GB/s via x16 configuration
- PAM-4 encoding
- FLIT (flow control unit)-based encoding
- Low-latency FEC and other mechanisms to improve bandwidth efficiency
As the latest specification progresses to final release, system architects, SoC designers, PCB developers and SI engineers are challenged as never before to implement bleeding edge PCIe 6.0 solutions. This is especially true as HPC, data center, cloud and AI edge applications increase in speed and density.
What’s tools are available for PCIe 6.0 development?
PCIe 6.0 from IP to Interconnect
Real-world PCIe 6.0 solutions requires many pieces. Key ingredients include IP, silicon, PCBs and high-speed interconnect. In previous blogs, Samtec and Synopsys have detailed PCIe 6.0 interoperability with technology demonstrations at DesignCon and the the AI Hardware Summit.
What really went in to these demos? Samtec and Synopsys are about to pop the hood.
Technical experts from Samtec and Synopsys will expand on technology demonstrations in a webinar entitled PCIe 6.0 From IP to Interconnect in High-Performance Computing. The webinar will be held on Wednesday, December 8, 2021, from 10:00 AM – 11:00 AM PST.
In this webinar, details include the latest developments in next-generation PCIe 6.0 solutions and interoperable technology from IP to interconnect in HPC. Additionally, practical signal channel design techniques and connectivity options will be highlighted.
For more information, please register for the webinar here.