System architects and design engineers are interested in bleeding-edge performance. In this new 112 Gbps PAM4 product demonstration, Samtec marries an SI Evaluation Kit for the new AcceleRate®HP interconnect system with a Synopsys 112 Gbps PAM4 transceiver test chip.
AcceleRate® HP is one of several Samtec connector systems rated at 112 Gbps PAM4, and it also provides outstanding design flexibility.
The test set-up emulates real-world, high data rate applications by routing differential pair signals from the Synopsys device through the AcceleRate HP High-Performance Arrays.
Ralph Page, Systems Architect at Samtec, walks us through the demo and review its performance. This took place at DesignCon 2021.
The signals travel through 6” of coaxial cable, to Samtec 1.85 mm compression mount jacks on the first SI Evaluation board, and then through a 2” trace to a mated set of right angle, or 90°, Samtec AcceleRate HP connector system.
These are the APM6 vertical array, and the right angle APF6 socket array.
The signals then exit the second PCB through more 1.85 mm compression mount jacks, through another 6” of coax cable, back through the Bulls Eye, and they return to the Synopsis transceiver test chip.
The overall channel loss is -32.5 dB at 28 GHz. The Samtec evaluation platform accounts for only a few of those dBs.
The eyes are wide open, and the Pre-FEC bit error rate is e-7. Of course, the Post-FEC bit error rate would be zero.
Samtec offers a growing portfolio of easy-to-use SI Evaluation Kits for testing many of Samtec’s high-performance interconnect solutions.
If you have questions about this product demonstration, or other high data rate, 112 Gbps PAM4 solutions, please contact us at SIG@Samtec.com