It is a bit surreal to think DesignCon 2020 went off right before world turned upside down just a few weeks after everyone got home. We have missed seeing customers face to face and are excited to have the opportunity to see some of you in the upcoming weeks! The show floor may not be back to full capacity and presentations will be a bit lighter this year. Samtec will be there and ready to talk about your new designs. In this DesignCon 2021 Preview we want to share with you some of the papers we will be presenting, or had a part in putting together.
Are you Ready?
Before we get too deep into the technical paper we want to make you are ready for the show!
Register Here for DesignCon 2021
Join Samtec at the Welcome Reception!
Find Samtec at Booth 907 during the exposition!
Check out the full Samtec schedule on our event landing page Here!
Not only does Samtec have amazing interconnect options we also have some of the brightest technologist and engineers on the market today! They have each contributed to papers and panel discussions to share some of that knowledge with you. (Make sure to save a link to our DesignCon 2021 landing page where we will update direct links to the presentations after the show)
DesignCon 2021 Preview Technical Presentations
Monday, August 16 kicks off the conference with boot camps, panel discussions and technical sessions (plus the amazing welcome reception, sponsored by Samtec mentioned above)!
Monday, August 16
4:45 PM – 6:00 PM Panel discussion “PCIe 6.0: New Challenges & New Tests for an Old Standard“
The consumer and market demand for higher data throughput has been pushing industries and standards to increase data rates. The evolution of other standards has also been pushing technologies such as PCIe to higher data rates. PCIe 5.0 with data rate of 32 GTPS had already introduced many Signal Integrity and design challenges. (Learn More or Attend the session Here)
Tuesday, August 17
8:00 AM – 8:40 AM “Specification-based IBIS-AMI model PCIe 5.0 32GT/s“
We will demonstrate how to convert electrical specification documents for PCIe 5.0 32GT/s and generate an equivalent IBIS-AMI model to represent the significant electrical signaling behaviors. (Learn More or Attend the session Here)
11:10 AM – 11:50 AM “A Case Study in the Development of a 112Gbps-PAM4 Silicon & Connector Test Platform”
The continued progression to higher data rates puts increasing demands on the design of practical serdes channels. At 112G-PAM4, the UI is only 17.86ps, and signal transmission in the PCB must be highly optimized for loss, reflections, crosstalk and power integrity. (Learn More or Attend the session Here)
2:00 PM – 2:40 PM “Hidden Secrets of IBIS Sampling Specifications“
The I/O Buffer Information Specification-Algorithmic Modeling Interface (IBIS-AMI) enables sharing of a model, which encompasses the complexity of the transmitter and receiver blocks. The IBIS-AMI model outputs an equalized waveform along with sampling information to the EDA tool. (Learn More or Attend the session Here)
3:00 PM – 3:40 PM “Design Case Study & Experimental Validation for a 100 Gb/s Per Lane C2M Link Using Channel Operating Margin“
The Chip-to-Module (C2M) interface as specified by the IEEE 802.3 Standard Working Group, and currently being updated for higher data rates, implements links that must perform up to 800 Gb/s (8 × 100 Gb/s) within the internet infrastructure physical layer. The design of these channels requires multiple engineering disciplines that fused together to create a comprehensive workflow. (Learn More or Attend the session Here)
4:00 PM – 5:15 PM Panel Discussion “Avoiding Disaster: Planning for Laminate Electrical Properties as a Function of Temperature”
How much variation should be expected and what should OEM designers of high-speed systems designers do to accommodate these variations in pre-prototype signal-integrity simulations? (Learn More or Attend the session Here)
Wednesday, August 18
9:00 AM – 9:40 AM “Impact of Power Plane Termination on System Noise“
To reduce power rail voltage fluctuations that could lead to noise emissions, it is critical to keep the power plane’s impedance below a target and minimize impedance peaks over frequency. Previous studies have shown that RC power plane termination can reduce power plane impedance peaks including on an electrically dense production board where decoupling capacitors would not fit near-critical memory components. (Learn More or Attend the session Here)
If you have made it this far you must be serious about our first DesignCon 2021 Preview! A second preview blog talking about our demonstrations will come out in the next week! As always if you have questions about anything you read above please reach out to our Technical Marketing Team!
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