Samtec is prepared for the fast-approaching technical renaissance with innovative Silicon-to-Silicon solutions that exceed standard connectivity demands. New architectures will require massive increases in transmission speeds, bandwidths, frequencies and densities. Samtec is addressing these challenges with a broad line of signal integrity optimized, high-performance interconnect and technology solutions, along with the highest level of expertise in the industry.
Below are the details from our demonstrations and presentations at DesignCon 2021.
Featured Demos – Samtec Booth 907
112G PAM4 with Alphawave
The innovative design of NovaRay combines extreme density and extreme performance, which is critical as system sizes decrease and speeds increase. The fully shielded differential pair design contributes to the industry-leading 4.0 Tbps aggregate data rate.
112G PAM4 with Xilinx
This inside-the-box, flyover demonstration highlights both Precision RF 70 GHz Bulls Eye and NovaRay NVAC cable assembly.
64G PAM4 (PCIe 6.0) and 112G PAM4 with Synopsys
This first demo features Samtec’s Gen-Z connector HSEC6-DV. Samtec’s 70 GHz Bulls Eye will carry the signal from the Synopsys PCIe 6.0 test chip to the mated edge card assembly. The second demo combines Samtec AcceleRate® HP High-Performance Arrays with a Synopsys 112G PAM4 transceiver test chip.
V-band/60GHz, Flexible waveguide with Vubiq
This proof-of-concept V-band demonstration is running actual 10 Gbps Ethernet modulated traffic at 60 GHz through Samtec’s flexible waveguides, using Vubiq’s Haul Pass V10G product mainboard and Analog Devices HMC 6300 and 6301 chipset.
Technical Presentations
Tuesday, August 17 • 8:00 AM – 8:40 AM
Specification-based IBIS-AMI model PCIe 5.0 32GT/s
We will demonstrate how to convert electrical specification documents for PCIe 5.0 32GT/s and generate an equivalent IBIS-AMI model to represent the significant electrical signaling behaviors.
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Tuesday, August 17 • 11:10 AM – 11:50 AM
A Case Study in the Development of a 112Gbps-PAM4 Silicon & Connector Test Platform
The continued progression to higher data rates puts increasing demands on the design of practical serdes channels. At 112G-PAM4, the UI is only 17.86ps, and signal transmission in the PCB must be highly optimized for loss, reflections, crosstalk and power integrity.
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Tuesday, August 17 • 2:00 PM – 2:40 PM
Hidden Secrets of IBIS Sampling Specifications
The I/O Buffer Information Specification-Algorithmic Modeling Interface (IBIS-AMI) enables sharing of a model, which encompasses the complexity of the transmitter and receiver blocks. The IBIS-AMI model outputs an equalized waveform along with sampling information to the EDA tool.
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Tuesday, August 17 • 3:00 PM – 3:40 PM
Design Case Study & Experimental Validation for a 100 Gb/s Per Lane C2M Link Using Channel Operating Margin
The Chip-to-Module (C2M) interface as specified by the IEEE 802.3 Standard Working Group, and currently being updated for higher data rates, implements links that must perform up to 800 Gb/s (8 × 100 Gb/s) within the internet infrastructure physical layer. The design of these channels requires multiple engineering disciplines that fused together to create a comprehensive workflow.
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Wednesday, August 18 • 9:00 AM – 9:40 AM
Impact of Power Plane Termination on System Noise
To reduce power rail voltage fluctuations that could lead to noise emissions, it is critical to keep the power plane’s impedance below a target and minimize impedance peaks over frequency. Previous studies have shown that RC power plane termination can reduce power plane impedance peaks including on an electrically dense production board where decoupling capacitors would not fit near-critical memory components.
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Panel Discussions
Monday, August 16 • 4:45 PM – 6:00 PM
Panel — PCIe 6.0: New Challenges & New Tests for an Old Standard
The consumer and market demand for higher data throughput has been pushing industries and standards to increase data rates. The evolution of other standards has also been pushing technologies such as PCIe to higher data rates. PCIe 5.0 with data rate of 32 GTPS had already introduced many Signal Integrity and design challenges.
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Tuesday, August 17 • 4:00 PM – 5:15 PM
Panel — Avoiding Disaster: Planning for Laminate Electrical Properties as a Function of Temperature
How much variation should be expected and what should OEM designers of high-speed systems designers do to accommodate these variations in pre-prototype signal-integrity simulations?
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