Techniques for Data Rates Beyond 200 Gbps: Best Paper
Three Samtec Authors Win DesignCon 2025 Best Paper Award
DesignCon 2025 has announced its Best Paper Awards winners, and three Samtec authors are honored alongside their colleagues from other organizations.
The paper, Beyond 200G: Brick Walls of 400G Links Per Lane, was written by Brandon Gore, Andrew Josephson, and Rich Mellitz of Samtec; Francesco de Paulis, University of L’Aquila; and Luis Boluna, John Calvin, Rick Rabinovich, and Mike Resso of Keysight. Best Paper Award Finalists are selected by the DesignCon Technical Program Committee, and winners are determined based on the quality of the presentations as judged by attendee feedback at the conference. This paper was presented at DesignCon 2025 by Andrew Josephson.
Design Improvements for the Datacenter
Applications such as artificial intelligence (AI) and machine learning (ML) are driving data rates beyond 200 Gb/s PAM4 per lane. In fact, AI high-performance-computing clusters have significantly impacted the physical infrastructure requirements of data center facilities. The changing landscape of platforms, equipment design, architecture topologies, power density requirements, and cooling demands all underscore the pressing need for new architectural designs.
Specifically, the physical layer performance of the data center must be improved by meeting many design challenges, including minimizing insertion loss and eliminating reflections while controlling the impedance environment throughout all copper interconnects. Moving to 400 Gb/s per lane requires a progression of materials, interconnects, and manufacturing methods as well as new system topologies.
This award-winning paper explores the challenges and some practical engineering solutions to fulfill the predicted 400 Gb/s per lane data rates necessary for AI/ML large language learning models.
Various design improvements for higher data rates are explored including new copper cable assemblies, better SERDES signal processing, and better control of the characteristic impedance of the channel. Design case studies show how to maintain an acceptable insertion loss in the 100 GHz range. The authors also review interconnect transition design to enhance channel performance.
The paper analyzes the pros and cons for links operating at 400 Gb/s per lane including the topics of potential obsolescence of components and media to enable the transmission of data with an acceptable bit error ratio (BER). Front-panel connectors such as QSFP and OSFP, in their different versions, may no longer have adequate performance because of their inherent wipe tail created at the point of contact between the connector spring and the PCB microstrip finger. This wipe can create resonances as low as 60 GHz, well below the Nyquist frequency of 106.25 GHz in the case of PAM4 encoding.
Several times in the past, copper cable solutions at increased bit rates were projected to be unfeasible, however, cable manufacturers were able to deliver acceptable solutions with a compromise of physical reach. This paper explains the details of potential candidates to replace traditional connectors, such as embedded electrical-to-optical converters using co-packaged assembly substrates.
Signal Integrity Center of Excellence
Samtec has created the Signal Integrity Center of Excellence area of its website to help you find the resources you need to develop your design. This section includes online design tools, technical resources, technical education, models, and videos. For specific questions, feel free to contact [email protected] to work directly with a technical expert.
More Information
Samtec Demonstrates New 1.6 Tbps OCP OAI EXP Module at SC24 – The Samtec Blog
110 GHz Test Solution Enables 224 Gbps PAM4 SerDes Characterization – The Samtec Blog
224G Test Platform Provides Scalability, Cost Benefits, Pathway to 448G – The Samtec Blog
First-of-a-Kind Demonstration of 200G Co-Packaged Copper Channel – The Samtec Blog
