Questions on Signal Integrity and Power Integrity Design
In a recent Samtec gEEk® spEEk episode, SI/PI gurus Scott McMorrow, Rich Mellitz, and Istvan Novak answered questions from the audience. Attendees asked questions on signal integrity and power integrity design that spoke to some emerging engineering challenges. In their responses, Scott, Rich, and Istvan emphasized the importance of rigorous analysis, careful tool characterization, and a deep understanding of underlying principles. You can listen to the entire discussion online. In the meantime, we have highlighted some of their responses below.
What is the recommended margin for signal integrity and power integrity designs?
The required margin in SI/PI designs depends heavily on specific project requirements and accumulated experience. While Design of Experiments (DOE) can be used to analyze and relate measured parameters to product quality and yield, it’s essential to consider business decisions regarding acceptable defect rates. Some engineers rely on intuition or extensive measurement campaigns to understand these relationships. Ultimately, determining the necessary margin is a complex interplay of analysis, experience, and business objectives.
When does vertical power delivery become more beneficial than horizontal power delivery?
While vertical power delivery offers advantages for high-current designs, a widespread shift depends on the availability of supporting infrastructure and components. A gradual transition is expected as current demands in designs reach the multi-hundred amp range. Factors like standardized footprints for vertical placement and the maturity of the technology also play a role in determining the break-even point. Right now it is really still in the experimental phase.
How can additive manufacturing be applied to signal integrity designs, and what are its limitations?
Currently, additive manufacturing in SI designs is primarily used for creating interconnects, replacing connectors, and fabricating small-volume PCB prototypes. However, material properties of 3D-printed components present challenges for high-speed, low-loss interconnects. Conductivity, dimensional accuracy, repeatability, and surface roughness remain significant concerns for high-frequency performance in the signal path. Opportunities do exist here for shielding. In the long term, advancements in printable materials and process control could expand the applicability of additive manufacturing in SI designs. It has a lot of potential, but once performance issues are addressed, volume manufacturing challenges may still remain.
What are the challenges in simulating SI/PI, and what steps can be taken to ensure accuracy?
Simulating accurately requires careful consideration of various factors, including model accuracy, computational resources, and the complexity of modern systems. Due to the difficulty of measuring every aspect of a system simultaneously, simulation becomes crucial. However, it’s imperative to characterize the simulator against known benchmarks and physical measurements to understand its error bounds and limitations—we cannot stress that enough. This characterization process helps avoid inaccurate results and ensures the simulation accurately reflects the real-world behavior of the system.
“How do you put a test point in Jell-O?”
Rich Mellitz
Why is there no formal specification or standard for power integrity?
Establishing a formal standard for power integrity is challenging due to the inherent difficulty in localizing power distribution networks. Unlike signal integrity, where signals can be isolated, power distribution affects the entire system. Additionally, silicon and package design information, crucial for accurate power integrity analysis, is often proprietary and not readily shared by manufacturers. This lack of standardization in power distribution networks makes it difficult to define universally applicable test points or compliance criteria. Or as Rich Mellitz said, “How do you put a test point in Jell-O?”
What are the consequences of placing power balls adjacent to signal balls in a differential pair within a BGA package?
Placing power balls directly next to signal balls in a differential pair can negatively impact signal integrity. This configuration disrupts the localized return path for the signals, leading to coupling into the power delivery network. This can introduce noise and degrade signal performance. If you have to do this, make sure you do it symmetrically and use grounds to carry the instantaneous return current. Ideally, ground balls should surround the differential pair for optimal signal integrity.
For a new SI designer focused on high-speed serial links, what key aspects of design should they prioritize learning?
New SI designers working with high-speed serial links should prioritize understanding via design and behavior. Mastering via characteristics, spacing, impedance control, and energy containment within the board are crucial for high-speed designs. (This becomes even more important when designing in close proximity to RF or power circuits as well as when dealing with EMC/EMI, but all of your work with localization will help you understand what is happening there.) Given the complexity of modern signal processing handled by integrated circuits, focusing on via optimization and minimizing signal distortion become key areas of expertise. “Stay away from noisy switches,” Rich Mellitz.
What are the negative implications of routing DDR signals near the edge of a PCB?
Routing DDR signals near the edge of a PCB can increase the risk of signal integrity issues due to reflections and crosstalk. The corners and edges of the board act as discontinuity points for power and ground planes, leading to signal reflections. Placing vias near these edges exacerbates the problem. Additionally, the reduced density of ground vias near the edges limits the return path for signals, increasing the potential for crosstalk. Bottom line: Keep your vias away from the edges and corners to avoid crosstalk (because it’s the area where we have fewer return path grounds).
More Information
Getting Help with Power Integrity – The Samtec Blog
Webinar: SerDes Common-Mode Noise: How Much is Too Much? | Samtec
