Samtec not only wants to design amazing products, but we also want to contribute to the electronics community as a whole. We do this by providing amazing customer service, hosting educational webinars, and by submitting papers for education tracks at key tradeshow. We are thrill when our engineers and technologist are recognized for their contributions through DesignCon’s Best Paper awards.
Samtec’s Best Paper Award for DesignCon 2021 is for;
This was authored by the following systems architects, signal integrity engineers, and all around great guys!
We could not have pull this off without the co-author support of Raj Mahadevan from Alphawave IP.
The Best Paper Abstract
The continued progression to higher data rates puts increasing demands on the design of practical serdes channels. At 112G-PAM4, the UI is only 17.86ps, and signal transmission in the PCB must be highly optimized for loss, reflections, crosstalk and power integrity. This paper describes the signal-integrity and power-integrity design process. Simulated performance is correlation to measured data.
Importance of the Case Study
Any time a test platform shows corrolation between the simulation and measurements this allows designers to accelerate thier timeline. Showing the iterative process and how lessons learned help guide the test platform will help other system architects on future designs. As more channels are being designed running 112 Gbps – PAM4 this design process and tolerance get tighter. If you work with designing channels at these speed I urge you to read through the paper linked above. If you have questions about its content or need help on your design reach out to SIG@Samtec.com
The Test Platform in Action
The test channel used in the Best Paper was shown at DesignCon 2021. Check out the full channel and performance as author Jean-Remy walks us through the demonstration.