56 Gbps PAM4
At DesignCon 2018, Matt Burns (Technical Marketing Manager of Samtec) and Ivan Madrigal (SerDes Systems Application Engineer at Xilinx®), walk us through a combined Xilinx-Samtec 56 Gbps PAM4 backplane demonstration.
One port of 56Gbps PAM4 PBRS31 data is sourced from the transmitter of the Xilinx test chip containing GTM transceivers. The data routes through high-performance RF jumpers to a test paddleboard made of Isola Tachyon laminate material, through a mated Samtec ExaMAX® high-speed backplane connector set, and then to a backplane also made of Isola Tachyon.
Between the two test paddleboards, the backplane, and the two ExaMAX mated backplane connector sets, there is approximately a 30” (76.2 cm) of trace length. This system mimics real-world, next-gen backplane applications found in data centers worldwide.
At the end of the signal path, the Xilinx software tools evaluate and monitor the test chip containing GTM transceivers. The Xilinx software tools control the GTM transceivers and visually display the signal margin going into the receiver. This channel had a BER of 5.29x10e-8. As Xilinx’s Steve Leibson points out in his Xcell Daily Blog, that’s the error rate before adding the error-reducing capabilities of FEC, which can drop the error rate by perhaps another ten orders of magnitude or more.
Here’s another quick video, from our friends at Xilinx, showing the demonstration.
The results achieved from this combined Xilinx/Samtec demonstration prove the viability of 56G PAM4 signals in next-gen backplane applications found in data center equipment.
The chip used was the Xilinx 56 Gbps PAM4 SerDes test chip. Xilinx has already announced the integration of GTM transceivers in their Virtex UltraScale+FPGAs. These test chips support data rates of up to 58 Gbps PAM4.
ExaMAX High-Speed Backplane Connector System
The ExaMAX contact system has two reliable points of contact at all times and minimizes residual stubs. They provide low mating force and excellent contact normal force.