At DesignCon 2024, attendees will be treated to a panel that explores the issues associated with designing, modeling, simulating, and measuring electronic systems operating at state-of-the-art speeds. The industry experts will also discuss the design and measurement methodologies needed that ensure simulations are accurate predictions of actual system behavior.
On Tuesday 30 January, Todd Westerhoff (Siemens EDA), Al Neves (Wild River Technology), Cathy Liu (Broadcom, Inc), Gary Lytle (Cadence), Jim Weaver (Arista Networks), and Scott McMorrow (Samtec) are participating in the DesignCon Panel – Extreme Confidence Simulation for 400-800G Signal Integrity Design.
I caught up with two of the panelists to get their impression of why this topic matters:
Todd Westerhoff: As good as it can be, simulation is only ever an idealized approximation of reality. The British Statistician George E.P. Box is commonly quoted as having said “All models are wrong, but some models are useful.”
The question with high-speed design modeling and simulation is: how well do the results we obtain predict how an actual system will behave?
As speeds increase and boards get denser, the physical effects that represent the difference between success and failure become more difficult to model and measure accurately. Yet, if we don’t take steps to ensure that our simulated results match physical reality, what can we hope to accomplish with design simulations? What’s the point in performing detailed simulation if we build something different than what we simulated? This panel will explore these topics.
Al Neves: This topic is extremely important because it is the critical path to success for designing high-speed digital systems in the 56-224G PAM4 realm. PAM4 encoding has placed additional demands on design performance due to the power penalty. Signal integrity issues directly impact jitter margins, which is a measure of potential bit errors.
As far as technical challenges, the problems are shared between usage and EDA performance. A critical usage issue is ensuring good material ID models (ones not based on data sheets). The Dk and Df values in laminate data sheets (the composite material used to create stackups) are IPC derived. This is a material properties approach, so it does not include electromagnetic influence from the copper (conductor losses) and pre-preg/core processing.
This panel covers 3-dimensional electromagnetic optimization, as you would use for connector launch optimization (Samtec) and design. We also plan to cover jitter analysis of simple and complicated serial links, semiconductor simulations, IBIS AMI modeling of SERDES, and post layout verification where large numbers of nets are simulated.
For more information on connector launch optimization see:
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