Decoding PCIe with Dolphin ICS

In the previous articles in this series, I explored how PCIe performance is increasingly defined by the physical channel. The next step is to look beyond the board itself. What happens when PCIe is extended across cables, enclosures, and complete systems?

At that point, PCIe stops being just a board-level interface and becomes a system-level fabric. Architecture and interconnect can no longer be considered independently.

PCIe Beyond the PCB

Traditional PCIe implementations assume short, controlled traces within a single system. That model breaks down as modern applications demand more compute, more accelerators, and greater flexibility in how resources are deployed.

Artificial intelligence, medical imaging, industrial vision, defense, and high-performance computing increasingly rely on architectures that extend beyond a single motherboard. GPUs, FPGAs, storage, and I/O must be distributed across multiple boards, chassis, or racks.

PCIe remains attractive because it offers high bandwidth, low latency, and native load-store semantics without protocol translation. Extending PCIe beyond the PCB fundamentally changes how systems are designed.

At the system scale, PCIe design is no longer just a channel problem. It becomes a co-design problem, where topology, switching, software, and interconnect must be developed together. Decisions at the physical layer directly influence system architecture, and vice versa.

Enabling Scalable PCIe Architectures with Dolphin

Samtec partner and customer Dolphin ICS addresses this challenge with a combination of commercial PCIe hardware and system-level software, enabling multi-node, multi-device architectures using standard PCIe technology. This includes adapter cards, switches, active backplanes, expansion systems, and external cabling for PCIe 3.0, PCIe 4.0 and PCIe 5.0.

The key differentiator is tight hardware and software integration. Dolphin’s eXpressWare platform enables DMA and PIO across cables and backplanes, hot add and remove without reboot, and device sharing across hosts.

This platform allows accelerators such as GPUs and FPGAs to be dynamically allocated across multiple hosts or systems with very low latency and no protocol overhead. The result is a PCIe-based architecture that behaves more like a tightly coupled cluster than a set of discrete systems.

When the Channel Becomes the System

As discussed earlier in this series, at PCIe 4.0 and PCIe 5.0 data rates the physical layer becomes a primary design constraint. That challenge increases significantly once links extend beyond the PCB.

Each connector, transition, and cable reduces channel margin and adds loss. These effects combine to create a much tighter operating window, where small degradations can determine whether a system meets performance targets.

Mechanical factors also become more significant. Vibration, thermal cycling, and repeated mating cycles can affect contact integrity over time. At high data rates, even small mechanical changes can have measurable electrical impact.

The interconnect is no longer passive. It defines the usable channel. If it is not engineered correctly, it limits the entire system regardless of silicon or software capability.

Engineering the System-Level Interconnect

Samtec’s role is to ensure that the physical layer supports the intended system architecture rather than constraining it.

High-speed board-to-board and cable interconnects used in platforms such as Dolphin’s are designed from a channel perspective. Connector geometry, materials, and plating are optimized for multi-gigabit data rates while maintaining mechanical robustness.

Validation is performed at the system level. Instead of idealized conditions, performance is characterized across complete channels and realistic use cases, including connectors, cables, and PCB interfaces.

This is particularly important in situations where systems must move from prototype to deployment. The same interconnect strategy must support validation, integration, and production scaling without introducing late-stage risk.

When the physical layer is engineered as part of the architecture, designers can focus on topology and performance rather than resolving signal integrity issues late in the cycle.

Co-Design in Practice

The combination of Dolphin and Samtec reflects how PCIe system design is changing at higher data rates.

At lower data rates, architecture and interconnect could often be treated separately. At PCIe 4.0 and PCIe 5.0 that separation introduces risk. Systems may work in theory but fail to deliver reliable performance in practice.

Aligning system architecture with a validated interconnect strategy from the outset reduces that risk.

Dolphin provides the scalable architecture, including switching and topology. Samtec ensures the physical channel supports that architecture under real-world conditions.

This alignment enables faster development, fewer late-stage changes, and more predictable system behavior. Connector selection becomes part of system engineering, not a final procurement decision.

From Channel to Cluster

PCIe design no longer ends at the PCB. As systems scale, the boundary between architecture and interconnect disappears.

Understanding signal integrity at the channel level is only the starting point. The challenge is maintaining it across complete systems, from connectors and cables to multi-node architectures.

From connector to cluster, the goal remains the same. To build PCIe systems that scale effectively, deliver consistent performance, and remain reliable over time.

You can read the first three parts of the Decoding PCIe series here:
Part 1: A Mechanical Engineer’s Perspective
Part 2: Controlling the PCIe Channel
Part 3: Choosing the Right Connector

To learn more about Samtec PCIe Technology, visit the homepage.