Samtec high-speed technologies for Silicon-to-Silicon optimization will be on display, including demonstrations of our state-of-the-art Product Demonstrator featuring several new products: NovaRay™, AcceleRate® HD, and Flyover QSFP28 to Direct Pluggable cable assembly. Other spotlight products include ExaMAX® 56 Gbps PAM4 backplane system, Flyover QSFP28 double-density cable assembly, and AcceleRate® 56 Gbps NRZ slim body cable system. Samtec is in booth #841.
About Samtec | Featured Products | Featured Events | Presentations | Passes
About Samtec
Samtec is an industry leader in Signal Integrity and micro solutions, and offers a broad line of electronic interconnects including IC-to-Board and IC Packaging, High-Speed Board-to-Board, High-Speed Cables, Mid-Board and Panel Optics, Flexible Stacking, and Micro/Rugged components and cables.
This enables us to provide overall “Silicon-to-Silicon” system optimization from the bare die to an interface 100 meters away and all interconnect points in between.
Silicon-to-Silicon System Optimization
Increasing data rates, denser systems, and shrinking product footprints challenge designers to meet their system signal integrity needs. Samtec’s Silicon-to-Silicon system optimization provides engineers the service, products, tools and resources to optimize the entire signal path from bare die to IC package and assembly to PCB to connectors and cable assemblies and back again. Learn more about Silicon-to-Silicon system optimization.
Featured Products
NovaRay™
Samtec’s NovaRay™ is an industry-leading high bandwidth, high-density interconnect system. The innovative pin-to-ground differential pair configuration enables very low crosstalk to 40 GHz+, tight impedance control, and minimal variance in data rate as stack heights increase. The system is 112 PAM4 capable and is rated up to 56 Gbps NRZ per channel.
It boasts an industry-leading aggregate average data rate of 1.33 Tbps per square inch. The 92 Ω impedance rating addresses both 85 and 100 Ω applications. An improved breakout region has been developed using a new offset signal-to-ground configuration.
AcceleRate® HD
Samtec’s AcceleRate® HD is a 0.635 mm pitch, multi-row interconnect system that provides an ultra-high density interface and next-generation bandwidth. It features up to 240 total I/Os in a mere 1.88 square inch (12.1 square cm) of PCB real estate.
The mated stack height is a low 5 mm, with 7 mm and 10 mm stack heights to follow. The system incorporates the Edge Rate® contact system, which is optimized for signal integrity performance. It is rated to 56 Gbps with PAM4 modulation.
AcceleRate® Cable Assembly
Samtec’s AcceleRate® cable assembly is the slimmest in the industry with a 7.6 mm body width ideal for closer proximity to the IC. The high-density 2-row design features 8 and 16 pair configurations on a 0.635 mm pitch for up to 92 pairs per square inch.
Rated to 56 Gbps PAM4, this assembly supports Samtec’s flyover technology by flying signals over lossy PCB via ultra-low skew twinax Eye Speed® cable. This proprietary co-extruded cable supports next-generation performance with extended reach and system flexibility.
Flyover QSFP28 Double Density
The Flyover QSFP28 Double Density form factor focuses on a next generation high-density, high-speed pluggable backward compatible module form factor. The system’s pluggable modules support double the aggregate bandwidth of conventional QSFP modules by adding a second row of contacts, which enable support for a 16 differential pair electrical interface.
The Samtec FQSFP-DD flyover product meets this challenge with greater performance margin compared to the QSFP-DD connector-to-PCB approach. As advanced 50 Gbps+ per channel ASIC and FPGA solutions hit the market, a next-generation flyover approach that overcomes the limitations of signal loss on a PCB trace continues to become more relevant.
High-Speed Backplane – ExaMAX® and XCede® HD
ExaMAX®
ExaMAX® Direct Mate Orthogonal solutions remove the mid-plane, which allows fabric cards and line cards to mate directly and ultimately giving system designers increased flexibility. This architecture increases airflow and improves thermal efficiencies throughout the chassis. It also improves signal integrity, with shorter trace lengths and fewer connector transitions.
Leading equipment vendors from across the data center industry are leveraging the advantages of DMO, including storage, server, networking and other applications.
XCede® HD
XCede® HD achieves significant space savings and flexibility on the backplane with a small form factor and modular design. A 1.80 mm pitch and up to 84 differential pairs per linear inch provide greater density than traditional backplane systems.
The modularity of XCede® HD gives designers the flexibility to create any configuration for a specific application. Modules include signal, power, guidance/keying and end wall options for increased system durability.
FireFly™ Micro Flyover System™
Samtec’s 28 Gbps FireFly™ optical engine brings its industry-leading density to the 100 Gbps Datacom/Telecom and HPC markets. Designed for interchangeability, FireFly™ copper and optical both use the same micro connector system with easy insertion/removal and trace routing.
Available in extended temperature and PCIe®-over-Fiber versions, FireFly™ supports the latest Ethernet, InfiniBand™and Fibre Channel protocol specifications.
Featured Events/Demos
Monday, January 29, 2018 | 1:00pm – 5:00pm | Rooms 209/210, Santa Clara Convention Center
Samtec is proud to sponsor the IEEE P370 Plugfest. Register for this event here.
Thursday, February 1, 2018 | 1:00pm | Ansys, Booth #747
Scott McMorrow, Samtec’s CTO of Signal Integrity Products, will be giving an in-booth presentation on Trailblazing Past 56G-PAM4 with Samtec Flyover™ solutions.
January 30 – February 1, 2018 | Keysight, Booth #725
An active 32-port demonstration of Samtec’s Flyover QSFP28 double-density (FQSFP-DD) to ARC6 56 Gbps NRZ slim body cable assembly will be on display throughout the show.
January 30 – February 1, 2018 | Texas Instruments, Booth #619
A demonstration of Samtec’s ExaMAX® High-Speed Backplane Connectors and TI reminders for 50+ Gbps PAM4 data rates will be on display throughout the show.
Presentations
Wednesday, January 31, 2018 | 11:00am – 11:45am
Effective Return Loss for 112 G and 56 G PAM4
Room: Ballroom B
Track Name: 04 System Co-Design: Modeling, Simulation, and Measurement Validation Electromagnetic Compatibility/Mitigating Interference
Description: This paper proposes using a pulse echo for time domain reflectometry (TDR) rather the commonly used step function echo. The echoed pulse response of a single symbol is convolved with the modulation signal levels to produce an effective reflection coefficient metric at a specified bit error ratio (BER). A conversion to dB presents effective return loss (ERL) in more familiar return loss units. ERL is a single value which replaces the commonly used frequency domain return loss (RL) masks. It makes RL grading simple, straightforward and meaningful.
Wednesday, January 31, 2018 | 2:00pm – 2:40pm
Designing DC-Blocking Capacitor Transitions to Enable 56 Gbps NRZ & 112 Gbps PAM4
Room: Ballroom F
Track Name: 08 Optimizing High-Speed Serial Design
Description: DC-blocking capacitors are required in almost all applications of high-speed SERDES in order to level shift the differential signal to the optimum operating point for receiver performance and to avoid DC ground loops. As we start the transition from 28G to 56G NRZ and 112G PAM4, it is crucial that the DC-blocking capacitor present a high bandwidth, near-reflectionless transition to the signal in order to maintain at least 32 GHz of effective interconnect bandwidth. In this paper, we discuss the steps necessary to generate a realistic, detailed capacitor model for data transmission and optimize its layout for an electrically transparent design.
Wednesday, January 31, 2018 | 3:45pm – 5:00pm
Panel – The 400G Ethernet Turn: The Rise and Fall of the Eye Diagram
Room: Ballroom F
Track Name: 10 High-Speed Signal Processing, Equalization, and Coding
Description: The eye diagram is the bread-and-butter tool in many areas of digital communication and signaling. It is a straightforward visual gauge of the signal quality. As signaling moves from NRZ to PAM4, from below 10 GBd to 25+ and 50+ GBd, Ethernet and other standards shifted away from eye diagram measurement to linear fitted pulse, SNDR, and other methods. Why this change? We discuss the reasons, the new methods and what worked well and what was difficult, the acceptance and the way forward in 50+ GBd electrical and 100 GBd optical. Then we ask, “Is this transition a general move?” It certainly is occurring differently in different standards, so we compare the very highest speed standards to the latest DDR memory buses.
Thursday, February 1, 2018 | 11:00am – 11:45am
A NIST Traceable PCB Kit for Evaluating the Accuracy of De-Embedding Algorithms and Corresponding Metrics
This paper has been chosen as a DesignCon 2018 Best Paper Award Finalist by the DesignCon 2018 Technical Program Committee
Room: Ballroom G
Track Name: 13 Applying Test and Measurement Methodology
Description: In this presentation, we will introduce the two de-embedding/fixture removal techniques that have been gaining traction in the industry (2x-Thru and 1x-Reflect) comparing them with other fixture removal techniques. We will then describe a NIST traceable methodology to evaluate the de-embedding accuracy of these techniques for single-ended and coupled differential applications using a series of PCB test coupons. We will also discuss the appropriate metrics needed to evaluate the accuracy of the de-embedding algorithms.
Thursday, February 1, 2018 | 2:50pm – 3:30pm
Improving TDECQ and SNDR for Better Characterization of Serial Data Signals and Path from Mask Test to TDEC, SNDR, and TDECQ Measurements
Room: Ballroom G
Track Name: 09 Measurement, Simulation, and Optimization of Jitter, Noise, and Timing to Minimize Errors
Description: The test of high-speed serial data signals has developed from mask test to TDEC, transmitter and dispersion eye closure. With signaling moving to PAM4, measurements move in two directions: SNDR for PAM4– signal to noise and distortion ratio, a transmitter test tool which sums noise and other non-compensable features into one figure-of-merit number; and the TDECQ, transmitter and dispersion eye closure penalty quaternary. We summarize these developments, and in an original work we show improvements for SNDR and TDECQ for the near future.
Thursday, February 1, 2018 | 3:45pm – 5:00pm
Panel – How to Avoid Getting Totally Skewed: Glass-Weave Skew in High-Speed Design
Room: Ballroom D
Track Name: 08 Optimizing High-Speed Serial Design
Description: The objective of this panel session is to guide design teams through the process of evaluating and selecting the right glass styles or design strategies for eliminating glass-weave skew for multi-gigabit, high-speed PCB designs. Several methods have been proposed, including choosing a glass style that minimizes resin windows, aligning trace direction to the fill/weft, routing each member of the pair at the same pitch as the glass fibers, mechanically spread glass, dual-ply glass, zigzag routing of differential pairs at a 10º angle to the weave, building each PCB with the artwork rotated at a 10º angle to the panel and weave, or using glass with a lower dielectric constant (closer to the resin Dk).
In this panel session, we’ll nail down the answers to this quintessential design concern once and for all – or entertain you while the experts slug it out!
Thursday, February 1, 2018 | 3:45pm – 5:00pm
Panel – 400G Test & Measurement Ready for the New Challenges Ahead
Room: Ballroom C
Track Name: 13 Applying Test and Measurement Methodology
Description: 400G Ethernet is now close to standardization and we are already seeing successful & exciting results from early field trials. Many of the novel aspects of 400G Ethernet pose significant test and measurement challenges and this presentation highlights the revolutionary aspects of 400G technology and how it drives new concepts in test and measurement. From PAM4 modulation in the electrical and optical domain to the challenges of validating margin in FEC based links the presentation explores how the T&M community within the Ethernet Alliance is ready to take 400G to widespread and pain-free deployment.
Passes
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